Micron HBM4 Custom (NVHBM): How Does It Differ From JEDEC in the Supply Chain?
[Fact] On 2026-03-16, Micron’s IR said HBM4 36GB 12H entered high-volume production and is designed for NVIDIA Vera Rubin. [Fact] On 2026-08-26, NVIDIA’s developer blog defined NVHBM as a custom HBM base-die technology designed and validated with leading memory vendors, and contrasted it with the JEDEC HBM4e standard interface. This post separates those two tracks—JEDEC-standard stacks vs custom NVHBM—and explains what a custom base die and controller actually signal (not volume), how a TSMC-foundry base die changes the chain versus Micron’s earlier in-house-base-die era (as secondary reporting describes it), and how SK hynix and Samsung differ in structure only. It does not invent NVHBM mass-production dates, market-share percentages, or price targets. Company bandwidth, power, and area percentages are mentioned only briefly as company releases when needed, and read as not independently verified.
What stage do a custom base die and controller actually confirm (no mass-production leap)?
One-line answer: Public materials confirm (1) Micron’s HBM4 high-volume claim for Vera Rubin and (2) NVIDIA’s definition of NVHBM as a co-designed/validated custom base die, controller, and PHY—not a JEDEC ratification date or a Micron NVHBM production quarter.
[Fact] An HBM stack typically places DRAM core dies on a bottom base die, linked with TSVs. The base die handles stack I/O and control and meets the accelerator (GPU/xPU) interface. JEDEC-standard HBM aligns that electrical and timing contract industry-wide; a custom path reworks the base die, controller, and PHY jointly with the accelerator vendor.
[Fact] NVIDIA’s 2026-08-26 post describes NVHBM as custom HBM base-die technology designed and validated with leading memory manufacturers, and as a package-level complement to NVLink Fusion (custom XPUs/CPUs into NVIDIA’s AI infrastructure and MGX rack-scale path). In the same article, NVIDIA says it moves the memory controller into the 3D HBM stack’s base die and uses a custom PHY on the main compute die, changing interface area and power budgets relative to JEDEC HBM4e. That is architecture and product narrative, not a third-party benchmark or shipment series.
[Company claim] NVIDIA’s developer blog presents bandwidth, power, area, and end-to-end gains versus standard HBM4e with accompanying percentages. This post focuses on supply-chain structure, so the detailed % list is omitted. Those figures are NVIDIA blog claims and have not been independently verified.
[Fact] Micron’s 2026-03-16 IR confirms HBM4 36GB 12H HVP, Vera Rubin design intent, volume shipments beginning in 1Q calendar 2026, and customer samples of 48GB 16H. [Company claim] The same IR also lists bandwidth, power-efficiency, and pin-speed figures, but they are not needed for the supply-chain structure angle here, so the detailed list is omitted. Those figures are Micron IR claims and have not been independently verified.
Supply-chain reading of “custom base die / controller”:
| Stage | Confirmed in public sources? | How to read it |
|---|---|---|
| Micron JEDEC-class HBM4 stack in HVP (36GB 12H, Vera Rubin design) | [Fact] 2026-03-16 Micron IR | HBM4 volume ≠ NVHBM volume |
| NVHBM = custom base die + controller-in-stack + custom PHY (NVIDIA definition) | [Fact] 2026-08-26 NVIDIA blog | Definition ≠ shipments |
| NVHBM bandwidth / power / area % | [Company claim] NVIDIA blog | NVIDIA blog claims; not independently verified |
| NVHBM JEDEC ratification date, Micron MP quarter, completed customer quals | Not in allowed sources | Do not invent |
| Micron HBM4 bandwidth / power % | [Company claim] IR footnotes | Micron IR claims; not independently verified |
“Custom is here” does not jump to revenue, share, or a filled production slot. What is public is an HVP message for the standard-era stack plus a custom base-die architecture and co-validation narrative.
How does a TSMC-foundry base die change packaging dependence structurally?
One-line answer: Versus the in-house base-die path associated with Micron’s HBM4 era in secondary reporting, HBM4E / NVHBM tilt toward a foundry logic base die (reported as TSMC), so qualification sits on a chain that binds memory, foundry, and the accelerator vendor—not memory alone.
[Fact] The 2026-03-16 Micron IR states HBM4 HVP, Vera Rubin design, and 16H samples. It does not, in that release body, declare whether the base die was built in-house or at a foundry. This post does not invent an “in-house” sentence inside that IR.
[Secondary reporting — structure] TheElec (Jeong Il Joo) reports that at Micron’s FY Q4 2026 earnings event (Sept 30 local), CTPO Scott J. DeBoer said both custom NVHBM and JEDEC-standard HBM4E are being developed with foundry-process base dies, unlike Micron HBM4, which used an in-house base die. The same piece says Micron is outsourcing the HBM4E base die to TSMC, that the die is believed to be 3 nm-class, and that HBM4E-based NVHBM uses the same approach. Core-die naming (HBM4 = 1β, HBM4E = 1γ) is also TheElec’s reporting. This is not Micron IR text. The “3 nm-class” line is explicitly a belief/estimate in secondary reporting—an estimate only, not officially confirmed. DIGITIMES (2026-10-02) covers the same outsourced-base-die / NVHBM theme as secondary color only.
Structural axes only:
- DRAM core dies — memory vendor fab bits and stack body.
- Logic base die — reported in-house for Micron HBM4 vs foundry logic for HBM4E/NVHBM (secondary).
- Accelerator-side PHY and package — NVIDIA’s custom PHY / controller placement must still clear CoWoS-class 2.5D site, wiring, power, and thermal budgets.
- Qualification path — closer to “ship a co-validated custom base-die + PHY combo” than “buy a JEDEC-compatible cube and drop it in,” per NVIDIA’s framing.
[Company claim] NVIDIA says NVLink Fusion customers can access NVHBM base dies validated with leading memory makers to ease integration and qualification bottlenecks. That is platform product logic, not proof of any one vendor’s allocation, yield, or margin.
For builders: JEDEC HBM is the near-common-socket stack; NVHBM is a cube built to accelerator-defined base-die and PHY rules that memory vendors and a logic foundry must meet together. That coupling’s existence is readable in public copy; volumes, share, and calendar cells are not in the sources allowed here.
How do SK hynix and Samsung differ in structure only?
One-line answer: All three supply HBM for AI accelerators; the public difference is who fabricates the base die and who defines the custom—not who “won.” No share percentages.
Micron (this post’s focus)
[Fact] 2026-03-16 IR: HBM4 36GB 12H HVP, Vera Rubin design.
[Fact] 2026-08-26 NVIDIA: NVHBM = custom base die validated with leading memory vendors (Micron is not named as sole supplier in that definition).
[Secondary] TheElec: HBM4 in-house base die; HBM4E / NVHBM foundry (TSMC-reported) base die.
SK hynix × TSMC (structure only)
[Fact] 2024-04-19 SK hynix Newsroom MOU: proprietary base dies through HBM3E; plan to adopt TSMC advanced logic for the HBM4 base die; optimize SK HBM with TSMC CoWoS®; respond to common customers. The MOU’s HBM4-from-2026 production frame is background only—this post does not retell the later HBM5–CoWoS award feature.
Samsung (structure only)
[Company claim / company release] Samsung Global Newsroom (2026-02-12) announced HBM4 mass production and commercial shipment, highlighting a 4 nm logic base die, Foundry–Memory DTCO, and in-house advanced packaging. Read that as a vertical-integration positioning (memory + foundry + packaging). Do not infer from that release alone whether a given customer accelerator lands on Samsung’s package or external CoWoS. Pin-speed and bandwidth percentages are omitted here; they are not needed for the structure comparison.
| Axis | Micron (public + secondary) | SK hynix (public) | Samsung (public) |
|---|---|---|---|
| Standard-stack message | HBM4 HVP / Vera Rubin design (IR) | HBM4 TSMC base die + CoWoS MOU | HBM4 MP / commercial shipment claim |
| Custom / base die | NVHBM = NVIDIA-defined custom base die; HBM4E/NVHBM foundry base (secondary) | TSMC logic base from HBM4 (official MOU) | 4 nm logic base via group foundry (company) |
| Packaging narrative | NVIDIA PHY/package story + (indirect) foundry | Explicit CoWoS optimization | In-house advanced packaging + DTCO emphasis |
| Not compared | Share, yield, customer mix, stock | Same | Same |
No winner declaration. Public material shows standard vs custom, in-house vs foundry base die, and accelerator-defined custom vs group vertical-integration claims.
What risks and uncertainties remain?
One-line answer: Custom definitions and HBM4 HVP are public; NVHBM production slots, confirmed foundry nodes, package sites, customer mix, and the gap between company % claims and independent measurement are not.
- Definition / validation ≠ NVHBM volume — NVIDIA’s post is architecture/platform narrative; Micron’s HVP line is HBM4. Do not invent an NVHBM MP date.
- Secondary foundry shift — TheElec/DIGITIMES TSMC and “3 nm-class” lines do not replace IR. Node, contract, and volume stay unconfirmed.
- Package, power, thermals — Company logic about smaller PHY / lower HBM power is separate from real CoWoS-class slots, cooling, and board schedules.
- Multi-vendor wording — NVIDIA says “leading memory vendors” (plural). Do not read exclusivity.
- Company % claims — Bandwidth, power, area, and end-to-end figures are company releases and have not been independently verified; do not treat them as measured fact.
- No earnings / stock frame — ASP, margin, ROI, targets, and share are out of scope.
FAQ
Is NVHBM a completely different product from JEDEC HBM4 / HBM4E?
Per NVIDIA’s framing, it references and contrasts with the JEDEC HBM4e standard interface while changing area, bandwidth, and power budgets via a custom base die, controller, and PHY. Allowed sources do not support a sentence that a separate JEDEC ratification for NVHBM is already complete.
Does Micron’s HBM4 volume production mean NVHBM is in volume?
No. The 2026-03-16 IR confirms HBM4 36GB 12H HVP and Vera Rubin design. Do not merge that into an NVHBM production claim.
If the base die is at TSMC, is Micron just an OEM?
Public materials do not justify an “OEM-only” label. Structurally, DRAM cores, stacks, and customer quals recombine with a foundry logic base die and advanced packaging. Value split and margins are not covered here.
Is this investment advice?
No. It is a structure note from public IR, NVIDIA’s developer blog, SK/Samsung official pages, and clearly labeled secondary reporting—not a buy or sell recommendation.
Sources
- Micron IR, HBM4 HVP for NVIDIA Vera Rubin (2026-03-16) — https://investors.micron.com/news/press-release/2026/Micron-in-High-Volume-Production-of-HBM4-Designed-for-NVIDIA-Vera-Rubin-PCIe-Gen6-SSD-and-SOCAMM2-03-16-2026/default.aspx
- NVIDIA Developer Blog, NVLink Fusion / NVHBM (2026-08-26) — https://developer.nvidia.com/blog/nvidia-nvlink-fusion-brings-nvhbm-to-next-generation-ai-infrastructure/
- TheElec (secondary), Micron NVHBM / outsourced base die — https://www.thelec.net/news/articleView.html?idxno=14372
- DIGITIMES (secondary), Micron NVHBM / TSMC custom HBM — https://www.digitimes.com/news/a20261002PD216/micron-hbm-dram-bandwidth-design.html
- SK hynix Newsroom, MOU with TSMC on HBM4 base die / CoWoS (2024-04-19) — https://news.skhynix.com/en/sk-hynix-partners-with-tsmc-to-strengthen-hbm-technological-leadership/
- Samsung Global Newsroom, HBM4 commercial shipment (2026-02-12) — https://news.samsung.com/global/samsung-ships-industry-first-commercial-hbm4-with-ultimate-performance-for-ai-computing
Related context (no retell): the Micron AI-server HBM bottleneck tutorial and the SK HBM5–CoWoS validation post are separate. This article stays on JEDEC standard vs NVHBM custom supply-chain structure.